Digital Design Solutions
for communications and signal processing
Radix-22 SDF FFT Core
This module implements a radix-22 single-path delay feedback FFT processor with configurable FFT lengths and I/O widths. The Figure 1 below shows the architecture of the design. The pipelined systolic architecture of the design processes 1 sample per cycle, e.g. 100Msps when clocked at 100MHz. The Table 1 below shows resource utilisations for 8-bit input, full-precision output (i.e. unscaled) FFTs with 10-bit twiddle-factors implemented on a Xilinx Spartan-6 FPGA.
References:
- Shousheng He and Mats Torkelson, "A New Approach to Pipeline FFT Processor", Department of Applied Electronics, Lund University, S-22100 Lund, Sweden.
- James W. Cooley and John W. Tukey, "An Algorithm for the Machine Calculation of Complex Fourier Series", Math, Comp., vol. 19, pp. 297-301, Apr. 1965.
XionLogic Open-source FFT Processor Library
- Download Verilog-2001 Source Code
- View table of contents
- View installation notes
- View change history
See also:
Figure 1: Radix-22 SDF FFT Architecture
| Radix-22 SDF FFT Processor Resource Utilisation Guide | |||
| Design Parameter | Value | Unit | |
| Target FPGA | Xilinx Spartan-6 LX25-2 | - | |
| Clock frequency constraint | 110 | MHz | |
| Twiddle-factor width | 10 | Bits | |
| Input data width | 8 | Bits | |
| Resource Type | 256-point FFT | 1024-point FFT | 4096-point FFT |
| Throughput @ 100MHz | 100Msps | 100Msps | 100Msps |
| Slices | 365 | 620 | 1224 |
| Flip-Flops | 697 | 927 | 1184 |
| LUTs | 1178 | 1987 | 4279 |
| B-RAMs | 1 | 2.5 | 7.5 |
| DSP48A1s | 12 | 16 | 20 |
Table 1: Radix-22 SDF FFT Processor Resource Utilisation Guide